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Progressive EDA solutions for System Level Design and Functional Verification
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News: Avery Design Systems Announces AMBA AXI and AHB Verification Solution ...
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Real Intent: Booth #722 Avery Design: Booth #1363 Mirabilis Design: Booth #1250 Exhibition hours: June 14th, 15th and 16th, 9:00 - 18:00 |
IEEE International High Level Design Validation and Test Workshop Panel: Clock Domain Verification Challenges 5:30- 6:30pm, Saturday, June 11, 2010 Pranav Ashar, CTO, Real Intent
Workshop for Women in EDA (WWEDA) 1:00-2:00pm, Monday, June 14, 2010 2:40-3:15pm, Monday, June 14, 2010 Exhibit Hall B, Booth #1562 Topic: Efficient and Practical Prevention of X-Related Bugs |
BlackForest EDA is focused on Functional Verification and System Design solutions to help our customers to maximize Verification Productivity and speed up System Analysis. The portfolio consists of solutions from our partners Avery Design Systems, Real Intent, Mirabilis Design, HDL Works and Dashcourses complemented by ASIC/FPGA Design Service partners.
Hot spots are:
'SimCluster' for partitioning of large RTL and Gate level simulations,
'PCI-Xactor' and 'SATA-Xactor' test-environment for PCIe and SATA/PATA designs.
'EnVision' Family of Products for transparent formal Verification.
'VisualSim' for System Level concept development and optimization.
'EASE' for graphical HDL entry.
Frontend System - ASCI/FPGA Design and Verification Services.
Training Courses for I/O, Storage and other advanced technologies.
Self running demonstrations:
Verify your IO pins between PCB and FPGA using IO Checker: Self running demonstration
Please check the websites of our partners for technical details:
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Avery Design Systems Announces AMBA AXI and AHB Verification Solution ...
Real Intent Ships Ascent 2.0 All-in-One Automatic Verification Software
Real Intent Ships Next Generation of Ascent Automatic Verification Software
Real Intent Appoints Carol Hallett as Vice President of Sales
Avery article in Embedded Computing Magazine
Formal tool able to verify false paths
Was wäre wenn und andere Analysen - Elektronik Praxis ( German )
Scripting language for System Level design
Simulation ersetzt Trial-and-Error - EETimes ( German )
BlackForest establishment - ElektronikNet ( German )
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PCI Express Controllers |
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| Serial ATA |
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| SOC Building Blocks |
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High speed serial interfaces:
PCI 2.2 / PCI-X 1.0 / PCI-X 2.0 / PCI Express
SATA I / SATA II / ATA/ATAPI-6 / CE-ATA
USB 3.0
AMBA 3.0 AXI / AMBA 2.0 AHB
